Driver IC ST7701S

  GENERAL DESCRIPTION 

 The ST7701S, a 16.7M-color System-on-Chip (SOC) driver LSI designed for small and medium sizes of TFT LCD display, is capable of supporting up to 480RGBX864 in resolution which can transmit graphic data without RAM. The 480-channel source driver has true 8-bit resolution, which generates 256 Gamma-corrected values by an internal D/A converter.

 The ST7701S is able to operate with low IO interface power supply and incorporate with several charge pumps to generate various voltage levels that form an on-chip power management system for gate driver and source driver. The built-in timing controller in ST7701S can support several interfaces for the diverse request of medium or small size portable display.ST7701S provides several system interfaces ,which include MIPI/RGB/SPI.For further power control ,the dynamic backlight control function basing on displaying image content is also supported.

  FEATURES

 Single chip WVGA a-Si TFT-LCD Controller/Driver without Display RAM 

  1. Display Resolution 

    a, 480*RGB (H) *864(V) (WVGA)

    b, 480*RGB (H) *854(V) 

    c, 480*RGB (H) *800(V) 

    d, 480*RGB (H) *720(V)

    e, 480*RGB (H) *640(V) (VGA)

    f, 480*RGB (H) *360(V) 

 2. LCD Driver Output Circuits 
    a. Display Features 

    b, Source Outputs: 480 RGB Channels

    c, Support gate control signals to gate driver in the panel

    d, Common Electrode Output 

  3. Display Colors (Color Mode) 

    a, Full Color mode : 16.7M-colors, RGB=(888) max., Idle Mode Off 

    b, Reduce color mode: 262K colors

    c, Reduce color mode: 65K colors 

    d, Idle Mode: 8-color, RGB=(111) 

  4. Programmable Pixel Color Format (Color Depth) for Various Display Data input Format 

    a,  24-bit/pixel: RGB=(888) 

    b, 18-bit/pixel: RGB=(666)

    c,  16-bit/pixel: RGB=(565) 

  5. Display Interface 

    a, 8 bit,9bit and 16 bit serial peripheral interface 
    b, 16/18/24 RGB Interface(VSYNC, HSYNC, DOTCLK, ENABLE, DB[17:0],Sync and DE mode)

    c, MIPI Display Serial Interface (DSI V1.01 r11 and D-PHY V1.0, 1 clock and 1 or 2 data lane pairs)

       Supports one data lane / maximum speed 800Mbps

       Supports two data lanes / maximum speed 550Mbps 

   6. Display Features 

     a, Programmable Partial Display Duty 

     b, CABC for saving current consumption 

     c, Color enhancement

  7. On Chip Build-In Circuits 

     a, DC/DC Converter

     b, Adjustable VCOM Generation 

     c, Non-Volatile (NV) Memory to Store Initial Register Setting and Factory Default Value (Module ID,

     d, Module Version, etc)

     e, Timing Controller 

     f, 4 preset Gamma curve with separated RGB Gamma setting 

  8. Build-In NV Memory for LCD Initial Register Setting 

      a, OTP to store VCOM and ID1~ID3 

  9. Driving Algorithm Support 

       a,1-dot/2-dot/3-dot/4-dot Inversion 

       b, Column Inversion 

       c, Zigzag Inversion

  10. Wide Supply Voltage Range 

       a, I/O Voltage (VDDI to DGND): 1.65V ~ 3.3V (VDDI≦VDD) 

       b, Analog Voltage (VDDA to AGND): 2.5V ~ 3.6V

       c, MIPI Voltage (VDDAM to VSSAM): 2.5V ~ 3.6V

  11. On-Chip Power System 

       a, Source Voltage (VAP (GVDD) to VAN (GVCL)): +3.64~6.5V, -1.05~-5V

       b, VCOM level: GND 

       c, Gate driver HIGH level (VGH to AGND): +11.5V ~ +17 V

       d, Gate driver LOW level (VGL to AGND): -12V ~ -7.6V

  12. Optimized layout for COG Assembly

        a, Operate temperature range: −30℃to +85℃

  13. Lower Power Consumption